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Introduction¶

Coresight is an umbrella of technologies allowing for the debugging of ARMbased SoC. It includes solutions for JTAG and HW assisted tracing. Thisdocument is concerned with the latter.

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HW assisted tracing is becoming increasingly useful when dealing with systemsthat have many SoCs and other components like GPU and DMA engines. ARM hasdeveloped a HW assisted tracing solution by means of different components, eachbeing added to a design at synthesis time to cater to specific tracing needs.Components are generally categorised as source, link and sinks and are(usually) discovered using the AMBA bus.

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“Sources” generate a compressed stream representing the processor instructionpath based on tracing scenarios as configured by users. From there the streamflows through the coresight system (via ATB bus) using links that are connectingthe emanating source to a sink(s). Sinks serve as endpoints to the coresightimplementation, either storing the compressed stream in a memory buffer orcreating an interface to the outside world where data can be transferred to ahost without fear of filling up the onboard coresight memory buffer.

At typical coresight system would look like this:

While on target configuration of the components is done via the APB bus,all trace data are carried out-of-band on the ATB bus. The CTM providesa way to aggregate and distribute signals between CoreSight components.

The coresight framework provides a central point to represent, configure andmanage coresight devices on a platform. This first implementation centers onthe basic tracing functionality, enabling components such ETM/PTM, funnel,replicator, TMC, TPIU and ETB. Future work will enable moreintricate IP blocks such as STM and CTI.

Acronyms and Classification¶

Acronyms:

PTM:

Program Trace Macrocell

ETM:

Embedded Trace Macrocell

STM:

System trace Macrocell

ETB:

Embedded Trace Buffer

ITM:

Instrumentation Trace Macrocell

TPIU:

Trace Port Interface Unit

TMC-ETR:

Trace Memory Controller, configured as Embedded Trace Router

TMC-ETF:

Trace Memory Controller, configured as Embedded Trace FIFO

CTI:

Cross Trigger Interface

Classification:

Source:

ETMv3.x ETMv4, PTMv1.0, PTMv1.1, STM, STM500, ITM

Link:

Funnel, replicator (intelligent or not), TMC-ETR

Sinks:

ETBv1.0, ETB1.1, TPIU, TMC-ETF

Misc:

CTI

Device Tree Bindings¶

See Documentation/devicetree/bindings/arm/coresight.txt for details.

As of this writing drivers for ITM, STMs and CTIs are not provided but areexpected to be added as the solution matures.

Framework and implementation¶

The coresight framework provides a central point to represent, configure andmanage coresight devices on a platform. Any coresight compliant device canregister with the framework for as long as they use the right APIs:

struct coresight_device *coresight_register(struct coresight_desc *desc);

void coresight_unregister(struct coresight_device *csdev);

The registering function is taking a structcoresight_desc*desc andregister the device with the core framework. The unregister function takesa reference to a structcoresight_device*csdev obtained at registration time.

If everything goes well during the registration process the new devices willshow up under /sys/bus/coresight/devices, as showns here for a TC2 platform:

The functions take a structcoresight_device, which looks like this:

The “coresight_dev_type” identifies what the device is, i.e, source link orsink while the “coresight_dev_subtype” will characterise that type further.

The structcoresight_ops is mandatory and will tell the framework how toperform base operations related to the components, each component havinga different set of requirement. For that structcoresight_ops_sink,structcoresight_ops_link and structcoresight_ops_source have beenprovided.

The next field structcoresight_platform_data*pdata is acquired by callingof_get_coresight_platform_data(), as part of the driver’s _probe routine andstructdevice*dev gets the device reference embedded in the amba_device:

Specific class of device (source, link, or sink) have generic operationsthat can be performed on them (see structcoresight_ops). The **groupsis a list of sysfs entries pertaining to operationsspecific to that component only. “Implementation defined” customisations areexpected to be accessed and controlled using those entries.

Device Naming scheme¶

The devices that appear on the “coresight” bus were named the same as theirparent devices, i.e, the real devices that appears on AMBA bus or the platform bus.Thus the names were based on the Linux Open Firmware layer naming convention,which follows the base physical address of the device followed by the devicetype. e.g:

However, with the introduction of ACPI support, the names of the realdevices are a bit cryptic and non-obvious. Thus, a new naming scheme wasintroduced to use more generic names based on the type of the device. Thefollowing rules apply:

Thus, with the new scheme the devices could appear as

Some of the examples below might refer to old naming scheme and someto the newer scheme, to give a confirmation that what you see on yoursystem is not unexpected. One must use the “names” as they appear onthe system under specified locations.

Topology Representation¶

Each CoreSight component has a connections directory which will containlinks to other CoreSight components. This allows the user to explore the tracetopology and for larger systems, determine the most appropriate sink for agiven source. The connection information can also be used to establishwhich CTI devices are connected to a given component. This directory contains anr_links attribute detailing the number of links in the directory.

For an ETM source, in this case etm0 on a Juno platform, a typicalarrangement will be:

Following the out port to funnel2:

And again to funnel0:

Finding the first sink tmc_etf0. This can be used to collect dataas a sink, or as a link to propagate further along the chain:

via funnel4:

and a replicator0:

Arriving at the final sink in the chain, tmc_etr0:

As described below, when using sysfs it is sufficient to enable a sink anda source for successful trace. The framework will correctly enable allintermediate links as required.

Note: cti_sys0 appears in two of the connections lists above.CTIs can connect to multiple devices and are arranged in a star topologyvia the CTM. See (CoreSight Embedded Cross Trigger (CTI & CTM).) [4] for further details.Looking at this device we see 4 connections:

How to use the tracer modules¶

There are two ways to use the Coresight framework:

1. using the perf cmd line tools.
2. interacting directly with the Coresight devices using the sysFS interface.

Preference is given to the former as using the sysFS interfacerequires a deep understanding of the Coresight HW. The following sectionsprovide details on using both methods.

1. Using the sysFS interface:

Before trace collection can start, a coresight sink needs to be identified.There is no limit on the amount of sinks (nor sources) that can be enabled atany given moment. As a generic operation, all device pertaining to the sinkclass will have an “active” entry in sysfs:

At boot time the current etm3x driver will configure the first addresscomparator with “_stext” and “_etext”, essentially tracing any instructionthat falls within that range. As such “enabling” a source will immediatelytrigger a trace capture:

Trace collection is stopped the same way:

The content of the ETB buffer can be harvested directly from /dev:

The file cstrace.bin can be decompressed using “ptm2human”, DS-5 or Trace32.

Following is a DS-5 output of an experimental loop that increments a variable upto a certain value. The example is simple and yet provides a glimpse of thewealth of possibilities that coresight provides.

2. Using perf framework:

Coresight tracers are represented using the Perf framework’s PerformanceMonitoring Unit (PMU) abstraction. As such the perf framework takes charge ofcontrolling when tracing gets enabled based on when the process of interest isscheduled. When configured in a system, Coresight PMUs will be listed whenqueried by the perf command line tool:

linaro@linaro-nano:~$ ./perf list pmu

List of pre-defined events (to be used in -e):

cs_etm// [Kernel PMU event]

linaro@linaro-nano:~$

Regardless of the number of tracers available in a system (usually equal to theamount of processor cores), the “cs_etm” PMU will be listed only once.

A Coresight PMU works the same way as any other PMU, i.e the name of the PMU islisted along with configuration options within forward slashes ‘/’. Since aCoresight system will typically have more than one sink, the name of the sink towork with needs to be specified as an event option.On newer kernels the available sinks are listed in sysFS under($SYSFS)/bus/event_source/devices/cs_etm/sinks/:

On older kernels, this may need to be found from the list of coresight devices,available under ($SYSFS)/bus/coresight/devices/:

As mentioned above in section “Device Naming scheme”, the names of the devices couldlook different from what is used in the example above. One must use the device namesas it appears under the sysFS.

The syntax within the forward slashes ‘/’ is important. The ‘@’ charactertells the parser that a sink is about to be specified and that this is the sinkto use for the trace session.

More information on the above and other example on how to use Coresight withthe perf tools can be found in the “HOWTO.md” file of the openCSD gitHubrepository [3].

2.1) AutoFDO analysis using the perf tools:

perf can be used to record and analyze trace of programs.

Execution can be recorded using ‘perf record’ with the cs_etm event,specifying the name of the sink to record to, e.g:

The ‘perf report’ and ‘perf script’ commands can be used to analyze execution,synthesizing instruction and branch events from the instruction trace.‘perf inject’ can be used to replace the trace data with the synthesized events.The –itrace option controls the type and frequency of synthesized events(see perf documentation).

Note that only 64-bit programs are currently supported - further work isrequired to support instruction decode of 32-bit Arm programs.

Generating coverage files for Feedback Directed Optimization: AutoFDO¶

‘perf inject’ accepts the –itrace option in which case tracing data isremoved and replaced with the synthesized events. e.g.

Below is an example of using ARM ETM for autoFDO. It requires autofdo(https://github.com/google/autofdo) and gcc version 5. The bubblesort example is from the AutoFDO tutorial (https://gcc.gnu.org/wiki/AutoFDO/Tutorial).

How to use the STM module¶

Using the System Trace Macrocell module is the same as the tracers - the onlydifference is that clients are driving the trace capture ratherthan the program flow through the code.

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As with any other CoreSight component, specifics about the STM tracer can befound in sysfs with more information on each entry being found in [1]:

Like any other source a sink needs to be identified and the STM enabled beforebeing used:

From there user space applications can request and use channels using the devfsinterface provided for that purpose by the generic STM API:

Details on how to use the generic STM API can be found here:- System Trace Module[2].

The CTI & CTM Modules¶

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The CTI (Cross Trigger Interface) provides a set of trigger signals betweenindividual CTIs and components, and can propagate these between all CTIs viachannels on the CTM (Cross Trigger Matrix).

A separate documentation file is provided to explain the use of these devices.(CoreSight Embedded Cross Trigger (CTI & CTM).) [4].

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